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https://github.com/nxp-imx/mwifiex.git
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a036032a76
Driver Bug Fixes: ----------------- 1. LF-6972: Updated the License to GPL-2.0 2. Incremented the driver version Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
374 lines
17 KiB
C
374 lines
17 KiB
C
/** @file mlan_sdio.h
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*
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* @brief This file contains definitions for SDIO interface.
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* driver.
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*
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*
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* Copyright 2008-2021 NXP
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*
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* This software file (the File) is distributed by NXP
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* under the terms of the GNU General Public License Version 2, June 1991
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* (the License). You may use, redistribute and/or modify the File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*
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*/
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/****************************************************
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Change log:
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****************************************************/
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#ifndef _MLAN_SDIO_H
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#define _MLAN_SDIO_H
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/** Block mode */
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#ifndef BLOCK_MODE
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#define BLOCK_MODE 1
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#endif
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/** Fixed address mode */
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#ifndef FIXED_ADDRESS
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#define FIXED_ADDRESS 0
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#endif
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/* Host Control Registers */
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/** Host Control Registers : Host to Card Event */
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#define HOST_TO_CARD_EVENT_REG 0x00
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/** Host Control Registers : Host terminates Command 53 */
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#define HOST_TERM_CMD53 (0x1U << 2)
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/** Host Control Registers : Host without Command 53 finish host */
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#define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
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/** Host Control Registers : Host power up */
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#define HOST_POWER_UP (0x1U << 1)
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/** Host Control Registers : Host power down */
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#define HOST_POWER_DOWN (0x1U << 0)
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/** Host Control Registers : Upload host interrupt RSR */
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#define UP_LD_HOST_INT_RSR (0x1U)
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#define HOST_INT_RSR_MASK 0xFF
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/** Host Control Registers : Upload command port host interrupt status */
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#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
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/** Host Control Registers : Download command port host interrupt status */
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#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
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/** Host Control Registers : Upload host interrupt mask */
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#define UP_LD_HOST_INT_MASK (0x1U)
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/** Host Control Registers : Download host interrupt mask */
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#define DN_LD_HOST_INT_MASK (0x2U)
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/** Host Control Registers : Cmd port upload interrupt mask */
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#define CMD_PORT_UPLD_INT_MASK (0x1U << 6)
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/** Host Control Registers : Cmd port download interrupt mask */
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#define CMD_PORT_DNLD_INT_MASK (0x1U << 7)
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/** Enable Host interrupt mask */
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#define HIM_ENABLE \
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(UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | CMD_PORT_UPLD_INT_MASK | \
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CMD_PORT_DNLD_INT_MASK)
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/** Disable Host interrupt mask */
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#define HIM_DISABLE 0xff
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/** Host Control Registers : Upload host interrupt status */
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#define UP_LD_HOST_INT_STATUS (0x1U)
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/** Host Control Registers : Download host interrupt status */
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#define DN_LD_HOST_INT_STATUS (0x2U)
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/** Host Control Registers : Download CRC error */
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#define DN_LD_CRC_ERR (0x1U << 2)
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/** Host Control Registers : Upload restart */
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#define UP_LD_RESTART (0x1U << 1)
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/** Host Control Registers : Download restart */
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#define DN_LD_RESTART (0x1U << 0)
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/** Card Control Registers : Command port upload ready */
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#define UP_LD_CP_RDY (0x1U << 6)
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/** Card Control Registers : Command port download ready */
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#define DN_LD_CP_RDY (0x1U << 7)
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/** Card Control Registers : Card I/O ready */
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#define CARD_IO_READY (0x1U << 3)
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/** Card Control Registers : CIS card ready */
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#define CIS_CARD_RDY (0x1U << 2)
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/** Card Control Registers : Upload card ready */
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#define UP_LD_CARD_RDY (0x1U << 1)
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/** Card Control Registers : Download card ready */
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#define DN_LD_CARD_RDY (0x1U << 0)
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/** Card Control Registers : Host power interrupt mask */
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#define HOST_POWER_INT_MASK (0x1U << 3)
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/** Card Control Registers : Abort card interrupt mask */
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#define ABORT_CARD_INT_MASK (0x1U << 2)
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/** Card Control Registers : Upload card interrupt mask */
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#define UP_LD_CARD_INT_MASK (0x1U << 1)
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/** Card Control Registers : Download card interrupt mask */
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#define DN_LD_CARD_INT_MASK (0x1U << 0)
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/** Card Control Registers : Power up interrupt */
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#define POWER_UP_INT (0x1U << 4)
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/** Card Control Registers : Power down interrupt */
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#define POWER_DOWN_INT (0x1U << 3)
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/** Card Control Registers : Power up RSR */
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#define POWER_UP_RSR (0x1U << 4)
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/** Card Control Registers : Power down RSR */
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#define POWER_DOWN_RSR (0x1U << 3)
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/** Card Control Registers : SD test BUS 0 */
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#define SD_TESTBUS0 (0x1U)
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/** Card Control Registers : SD test BUS 1 */
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#define SD_TESTBUS1 (0x1U)
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/** Card Control Registers : SD test BUS 2 */
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#define SD_TESTBUS2 (0x1U)
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/** Card Control Registers : SD test BUS 3 */
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#define SD_TESTBUS3 (0x1U)
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/** Port for registers */
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#define REG_PORT 0
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/** Port for memory */
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#define MEM_PORT 0x10000
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/** Ctrl port */
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#define CTRL_PORT 0
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/** Ctrl port mask */
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#define CTRL_PORT_MASK 0x0001
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/** Card Control Registers : cmd53 new mode */
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#define CMD53_NEW_MODE (0x1U << 0)
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/** Card Control Registers : cmd53 tx len format 1 (0x10) */
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#define CMD53_TX_LEN_FORMAT_1 (0x1U << 4)
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/** Card Control Registers : cmd53 tx len format 2 (0x20)*/
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#define CMD53_TX_LEN_FORMAT_2 (0x1U << 5)
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/** Card Control Registers : cmd53 rx len format 1 (0x40) */
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#define CMD53_RX_LEN_FORMAT_1 (0x1U << 6)
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/** Card Control Registers : cmd53 rx len format 2 (0x80)*/
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#define CMD53_RX_LEN_FORMAT_2 (0x1U << 7)
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#define CMD_PORT_RD_LEN_EN (0x1U << 2)
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/* Card Control Registers : cmd port auto enable */
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#define CMD_PORT_AUTO_EN (0x1U << 0)
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/* Command port */
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#define CMD_PORT_SLCT 0x8000
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/** Misc. Config Register : Auto Re-enable interrupts */
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#define AUTO_RE_ENABLE_INT MBIT(4)
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/** Enable GPIO-1 as a duplicated signal of interrupt as appear of SDIO_DAT1*/
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#define ENABLE_GPIO_1_INT_MODE 0x88
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/** Scratch reg 3 2 : Configure GPIO-1 INT*/
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#define SCRATCH_REG_32 0xEE
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/** Event header Len*/
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#define MLAN_EVENT_HEADER_LEN 8
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/** SDIO byte mode size */
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#define MAX_BYTE_MODE_SIZE 512
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/** The base address for packet with multiple ports aggregation */
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#define SDIO_MPA_ADDR_BASE 0x1000
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/** SDIO Tx aggregation in progress ? */
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#define MP_TX_AGGR_IN_PROGRESS(a) (a->pcard_sd->mpa_tx.pkt_cnt > 0)
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/** SDIO Tx aggregation buffer room for next packet ? */
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#define MP_TX_AGGR_BUF_HAS_ROOM(a, mbuf, len) \
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(((a->pcard_sd->mpa_tx.buf_len) + len) <= \
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(a->pcard_sd->mpa_tx.buf_size))
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/** Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
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#define MP_TX_AGGR_BUF_PUT(a, mbuf, port) \
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do { \
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pmadapter->callbacks.moal_memmove( \
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a->pmoal_handle, \
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&a->pcard_sd->mpa_tx.buf[a->pcard_sd->mpa_tx.buf_len], \
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mbuf->pbuf + mbuf->data_offset, mbuf->data_len); \
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a->pcard_sd->mpa_tx.buf_len += mbuf->data_len; \
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a->pcard_sd->mpa_tx.mp_wr_info[a->pcard_sd->mpa_tx.pkt_cnt] = \
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*(t_u16 *)(mbuf->pbuf + mbuf->data_offset); \
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if (!a->pcard_sd->mpa_tx.pkt_cnt) { \
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a->pcard_sd->mpa_tx.start_port = port; \
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} \
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a->pcard_sd->mpa_tx.ports |= (1 << port); \
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a->pcard_sd->mpa_tx.pkt_cnt++; \
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} while (0)
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#define MP_TX_AGGR_BUF_PUT_NONEWMODE(a, mbuf, port) \
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do { \
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pmadapter->callbacks.moal_memmove( \
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a->pmoal_handle, \
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&a->pcard_sd->mpa_tx.buf[a->pcard_sd->mpa_tx.buf_len], \
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mbuf->pbuf + mbuf->data_offset, mbuf->data_len); \
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a->pcard_sd->mpa_tx.buf_len += mbuf->data_len; \
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a->pcard_sd->mpa_tx.mp_wr_info[a->pcard_sd->mpa_tx.pkt_cnt] = \
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*(t_u16 *)(mbuf->pbuf + mbuf->data_offset); \
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if (!a->pcard_sd->mpa_tx.pkt_cnt) { \
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a->pcard_sd->mpa_tx.start_port = port; \
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} \
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if (a->pcard_sd->mpa_tx.start_port <= port) { \
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a->pcard_sd->mpa_tx.ports |= \
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(1 << (a->pcard_sd->mpa_tx.pkt_cnt)); \
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} else { \
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a->pcard_sd->mpa_tx.ports |= \
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(1 << (a->pcard_sd->mpa_tx.pkt_cnt + 1 + \
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(a->pcard_sd->max_ports - \
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a->pcard_sd->mp_end_port))); \
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} \
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a->pcard_sd->mpa_tx.pkt_cnt++; \
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} while (0)
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#define MP_TX_AGGR_BUF_PUT_SG(a, mbuf, port) \
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do { \
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a->pcard_sd->mpa_tx.buf_len += mbuf->data_len; \
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a->pcard_sd->mpa_tx.mp_wr_info[a->pcard_sd->mpa_tx.pkt_cnt] = \
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*(t_u16 *)(mbuf->pbuf + mbuf->data_offset); \
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a->pcard_sd->mpa_tx.mbuf_arr[a->pcard_sd->mpa_tx.pkt_cnt] = \
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mbuf; \
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if (!a->pcard_sd->mpa_tx.pkt_cnt) { \
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a->pcard_sd->mpa_tx.start_port = port; \
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} \
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a->pcard_sd->mpa_tx.ports |= (1 << port); \
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a->pcard_sd->mpa_tx.pkt_cnt++; \
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} while (0)
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#define MP_TX_AGGR_BUF_PUT_SG_NONEWMODE(a, mbuf, port) \
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do { \
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a->pcard_sd->mpa_tx.buf_len += mbuf->data_len; \
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a->pcard_sd->mpa_tx.mp_wr_info[a->pcard_sd->mpa_tx.pkt_cnt] = \
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*(t_u16 *)(mbuf->pbuf + mbuf->data_offset); \
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a->pcard_sd->mpa_tx.mbuf_arr[a->pcard_sd->mpa_tx.pkt_cnt] = \
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mbuf; \
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if (!a->pcard_sd->mpa_tx.pkt_cnt) { \
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a->pcard_sd->mpa_tx.start_port = port; \
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} \
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if (a->pcard_sd->mpa_tx.start_port <= port) { \
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a->pcard_sd->mpa_tx.ports |= \
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(1 << (a->pcard_sd->mpa_tx.pkt_cnt)); \
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} else { \
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a->pcard_sd->mpa_tx.ports |= \
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(1 << (a->pcard_sd->mpa_tx.pkt_cnt + 1 + \
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(a->pcard_sd->max_ports - \
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a->pcard_sd->mp_end_port))); \
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} \
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a->pcard_sd->mpa_tx.pkt_cnt++; \
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} while (0)
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/** SDIO Tx aggregation limit ? */
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#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
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((a->pcard_sd->mpa_tx.pkt_cnt) == (a->pcard_sd->mpa_tx.pkt_aggr_limit))
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#define MP_TX_AGGR_PORT_LIMIT_REACHED(a) \
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((a->pcard_sd->curr_wr_port < a->pcard_sd->mpa_tx.start_port) && \
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(((a->pcard_sd->max_ports - a->pcard_sd->mpa_tx.start_port) + \
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a->pcard_sd->curr_wr_port) >= a->pcard_sd->mp_aggr_pkt_limit))
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/** Reset SDIO Tx aggregation buffer parameters */
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#define MP_TX_AGGR_BUF_RESET(a) \
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do { \
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memset(a, a->pcard_sd->mpa_tx.mp_wr_info, 0, \
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sizeof(a->pcard_sd->mpa_tx.mp_wr_info)); \
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a->pcard_sd->mpa_tx.pkt_cnt = 0; \
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a->pcard_sd->mpa_tx.buf_len = 0; \
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a->pcard_sd->mpa_tx.ports = 0; \
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a->pcard_sd->mpa_tx.start_port = 0; \
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} while (0)
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/** SDIO Rx aggregation limit ? */
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#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
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(a->pcard_sd->mpa_rx.pkt_cnt == a->pcard_sd->mpa_rx.pkt_aggr_limit)
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/** SDIO Rx aggregation port limit ? */
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/** this is for test only, because port 0 is reserved for control port */
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/* #define MP_RX_AGGR_PORT_LIMIT_REACHED(a) (a->curr_rd_port == 1) */
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/* receive packets aggregated up to a half of mp_end_port */
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/* note: hw rx wraps round only after port (MAX_PORT-1) */
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#define MP_RX_AGGR_PORT_LIMIT_REACHED(a) \
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(((a->pcard_sd->curr_rd_port < a->pcard_sd->mpa_rx.start_port) && \
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(((a->pcard_sd->max_ports - a->pcard_sd->mpa_rx.start_port) + \
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a->pcard_sd->curr_rd_port) >= (a->pcard_sd->mp_end_port >> 1))) || \
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((a->pcard_sd->curr_rd_port - a->pcard_sd->mpa_rx.start_port) >= \
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(a->pcard_sd->mp_end_port >> 1)))
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#define MP_RX_AGGR_PORT_LIMIT_REACHED_NONEWMODE(a) \
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((a->pcard_sd->curr_rd_port < a->pcard_sd->mpa_rx.start_port) && \
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(((a->pcard_sd->max_ports - a->pcard_sd->mpa_rx.start_port) + \
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a->pcard_sd->curr_rd_port) >= a->pcard_sd->mp_aggr_pkt_limit))
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/** SDIO Rx aggregation in progress ? */
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#define MP_RX_AGGR_IN_PROGRESS(a) (a->pcard_sd->mpa_rx.pkt_cnt > 0)
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/** SDIO Rx aggregation buffer room for next packet ? */
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#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
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((a->pcard_sd->mpa_rx.buf_len + rx_len) <= a->pcard_sd->mpa_rx.buf_size)
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/** Prepare to copy current packet from card to SDIO Rx aggregation buffer */
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#define MP_RX_AGGR_SETUP(a, mbuf, port, rx_len) \
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do { \
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a->pcard_sd->mpa_rx.buf_len += rx_len; \
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if (!a->pcard_sd->mpa_rx.pkt_cnt) { \
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a->pcard_sd->mpa_rx.start_port = port; \
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} \
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a->pcard_sd->mpa_rx.ports |= (1 << port); \
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a->pcard_sd->mpa_rx.mbuf_arr[a->pcard_sd->mpa_rx.pkt_cnt] = \
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mbuf; \
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a->pcard_sd->mpa_rx.len_arr[a->pcard_sd->mpa_rx.pkt_cnt] = \
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rx_len; \
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a->pcard_sd->mpa_rx.pkt_cnt++; \
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} while (0)
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#define MP_RX_AGGR_SETUP_NONEWMODE(a, mbuf, port, rx_len) \
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do { \
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a->pcard_sd->mpa_rx.buf_len += rx_len; \
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if (!a->pcard_sd->mpa_rx.pkt_cnt) { \
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a->pcard_sd->mpa_rx.start_port = port; \
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} \
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if (a->pcard_sd->mpa_rx.start_port <= port) { \
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a->pcard_sd->mpa_rx.ports |= \
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(1 << (a->pcard_sd->mpa_rx.pkt_cnt)); \
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} else { \
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a->pcard_sd->mpa_rx.ports |= \
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(1 << (a->pcard_sd->mpa_rx.pkt_cnt + 1)); \
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} \
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a->pcard_sd->mpa_rx.mbuf_arr[a->pcard_sd->mpa_rx.pkt_cnt] = \
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mbuf; \
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a->pcard_sd->mpa_rx.len_arr[a->pcard_sd->mpa_rx.pkt_cnt] = \
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rx_len; \
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a->pcard_sd->mpa_rx.pkt_cnt++; \
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} while (0);
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/** Reset SDIO Rx aggregation buffer parameters */
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#define MP_RX_AGGR_BUF_RESET(a) \
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do { \
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a->pcard_sd->mpa_rx.pkt_cnt = 0; \
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a->pcard_sd->mpa_rx.buf_len = 0; \
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a->pcard_sd->mpa_rx.ports = 0; \
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a->pcard_sd->mpa_rx.start_port = 0; \
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} while (0)
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/** aggr buf size 32k */
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#define SDIO_MP_AGGR_BUF_SIZE_32K (32768)
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/** max aggr buf size 64k-256 */
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#define SDIO_MP_AGGR_BUF_SIZE_MAX (65280)
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extern mlan_adapter_operations mlan_sdio_ops;
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/** Probe and initialization function */
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mlan_status wlan_sdio_probe(pmlan_adapter pmadapter);
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mlan_status wlan_get_sdio_device(pmlan_adapter pmadapter);
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mlan_status wlan_send_mp_aggr_buf(mlan_adapter *pmadapter);
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mlan_status wlan_re_alloc_sdio_rx_mpa_buffer(mlan_adapter *pmadapter);
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void wlan_decode_spa_buffer(mlan_adapter *pmadapter, t_u8 *buf, t_u32 len);
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t_void wlan_sdio_deaggr_rx_pkt(pmlan_adapter pmadapter, mlan_buffer *pmbuf);
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/** Transfer data to card */
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mlan_status wlan_sdio_host_to_card(mlan_adapter *pmadapter, t_u8 type,
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mlan_buffer *mbuf, mlan_tx_param *tx_param);
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mlan_status wlan_set_sdio_gpio_int(pmlan_private priv);
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mlan_status wlan_cmd_sdio_gpio_int(pmlan_private pmpriv,
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HostCmd_DS_COMMAND *cmd, t_u16 cmd_action,
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t_void *pdata_buf);
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mlan_status wlan_reset_fw(pmlan_adapter pmadapter);
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#endif /* _MLAN_SDIO_H */
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