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https://github.com/nxp-imx/mwifiex.git
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a036032a76
Driver Bug Fixes: ----------------- 1. LF-6972: Updated the License to GPL-2.0 2. Incremented the driver version Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
501 lines
18 KiB
C
501 lines
18 KiB
C
/** @file mlan_pcie.h
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*
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* @brief This file contains definitions for PCIE interface.
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* driver.
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*
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*
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* Copyright 2008-2021 NXP
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*
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* This software file (the File) is distributed by NXP
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* under the terms of the GNU General Public License Version 2, June 1991
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* (the License). You may use, redistribute and/or modify the File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*
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*/
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/********************************************************
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Change log:
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02/01/2012: initial version
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********************************************************/
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#ifndef _MLAN_PCIE_H_
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#define _MLAN_PCIE_H_
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/** Tx DATA */
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#define ADMA_TX_DATA 0
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/** Rx DATA */
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#define ADMA_RX_DATA 1
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/** EVENT */
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#define ADMA_EVENT 2
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/** CMD */
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#define ADMA_CMD 3
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/** CMD RESP */
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#define ADMA_CMDRESP 4
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/** ADMA direction */
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#define ADMA_HOST_TO_DEVICE 0
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/** ADMA direction Rx */
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#define ADMA_DEVICE_TO_HOST 1
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/** Direct Program mode */
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#define DMA_MODE_DIRECT 0
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/** Single descriptor mode */
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#define DMA_MODE_SINGLE_DESC 1
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/** dual discriptor mode */
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#define DMA_MODE_DUAL_DESC 2
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/** descriptor mode: ring mode */
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#define DESC_MODE_RING 0
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/** descriptor mode: chain mode */
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#define DESC_MODE_CHAIN 1
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/** DMA size start bit */
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#define DMA_SIZE_BIT 16
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/** DMA size mask */
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#define DMA_SIZE_MASK 0xffff0000
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/** Descriptor mode */
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#define DESC_MODE_MASK 0x0004
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/** DMA MODE MASK */
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#define DMA_MODE_MASK 0x0003
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/** Dest Num Descriptor start bits */
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#define DST_NUM_DESC_BIT 12
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/** Destination Num of Descriptor mask */
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#define DST_NUM_DESC_MASK 0xf000
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/** Src Num Descriptor start bits */
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#define SRC_NUM_DESC_BIT 8
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/** Destination Num of Descriptor mask */
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#define SRC_NUM_DESC_MASK 0x0f00
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/** Virtual Q priority mask */
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#define Q_PRIO_WEIGHT_MASK 0x00f0
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/** DMA cfg register offset*/
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#define ADMA_DMA_CFG 0x0000
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/** source base low */
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#define ADMA_SRC_LOW 0x0004
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/** source base high */
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#define ADMA_SRC_HIGH 0x0008
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/** destination base low */
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#define ADMA_DST_LOW 0x000C
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/** destination base high */
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#define ADMA_DST_HIGH 0x0010
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/** source rd/wr pointer */
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#define ADMA_SRC_RW_PTR 0x0014
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/** destination rd/wr pointer */
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#define ADMA_DST_RW_PTR 0x0018
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/** interrupt direction mapping reg, for each virtual Q, used for
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* dual-descriptor only, only valid for Q0 */
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#define ADMA_INT_MAPPING 0x001C
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/** destination interrupt to device */
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#define DEST_INT_TO_DEVICE MBIT(0)
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/** destination interrupt to host */
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#define DEST_INT_TO_HOST MBIT(1)
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/** interrupt pending status for each virtual Q, only valid for Q0 */
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#define ADMA_INT_PENDING 0x0020
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/** Default ADMA INT mask, We only enable dma done */
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#define DEF_ADMA_INT_MASK MBIT(0)
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/** source interrupt status mask reg */
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#define ADMA_SRC_INT_STATUS_MASK 0x0024
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/** source interrupt mask reg */
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#define ADMA_SRC_INT_MASK 0x0028
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/** source interrupt status reg */
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#define ADMA_SRC_INT_STATUS 0x002C
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/** destination interrupt status mask reg */
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#define ADMA_DST_INT_STATUS_MASK 0x0030
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/** destination interrupt mask reg */
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#define ADMA_DST_INT_MASK 0x0034
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/** destination interrupt status reg */
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#define ADMA_DST_INT_STATUS 0x0038
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/** DMA cfg2 register */
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#define ADMA_DMA_CFG2 0x003C
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/** ADMA_MSI_LEGACY_DST_DMA_DONE_INT_BYPASS_EN */
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#define ADMA_MSI_LEGACY_DST_DMA_DONE_INT_BYPASS_EN MBIT(22)
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/** ADMA_MSI_LEGACY_SRC_DMA_DONE_INT_BYPASS_EN */
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#define ADMA_MSI_LEGACY_SRC_DMA_DONE_INT_BYPASS_EN MBIT(21)
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/* If this bit is set, MSIX trigger event will be from DST, other wise MSIX
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* trigger event will be from SRC */
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#define ADMA_MSIX_INT_SRC_DST_SEL MBIT(20)
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/** Enable MSI/Legacy for this Queue */
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#define ADMA_MSI_LEGACY_ENABLE MBIT(19)
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/** Enable MSIX for this queue */
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#define ADMA_MSIX_ENABLE MBIT(18)
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/** ADMA_DST_DMA_DONE_INT_BYPASS_EN */
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#define ADMA_DST_DMA_DONE_INT_BYPASS_EN MBIT(17)
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/** SRC_DMA_DONE_INT_BYPASS_EN */
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#define ADMA_SRC_DMA_DONE_INT_BYPASS_EN MBIT(16)
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/* Destination Read Pointer Memory Copy Enable */
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#define ADMA_DST_RPTR_MEM_COPY_EN MBIT(11)
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/* Source Read Pointer Memory Copy Enable */
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#define ADMA_SRC_RPTR_MEM_COPY_EN MBIT(10)
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/** Destination address is host */
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#define ADMA_DST_ADDR_IS_HOST MBIT(2)
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/** Source address is host */
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#define ADMA_SRC_ADDR_IS_HOST MBIT(1)
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/** DMA cfg3 register */
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#define ADMA_DMA_CFG3 0x0040
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/** ADMA Queue pointer clear */
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#define ADMA_Q_PTR_CLR MBIT(0)
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/** source rd ptr address low */
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#define ADMA_SRC_RD_PTR_LOW 0x0044
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/** source rd ptr address high */
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#define ADMA_SRC_RD_PTR_HIGH 0x0048
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/** destination rd ptr address low */
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#define ADMA_DST_RD_PTR_LOW 0x004C
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/** destination rd ptr address high */
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#define ADMA_DST_RD_PTR_HIGH 0x0050
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/** source active interrupt mask */
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#define ADMA_SRC_ACTV_INT_MASK 0x0054
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/** destination active interrupt mask */
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#define ADMA_DST_ACTV_INT_MASK 0x0058
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/** Read pointer start from bit 16 */
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#define ADMA_RPTR_START 16
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/** write pointer start from bit 0 */
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#define ADMA_WPTR_START 0
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/** Tx/Rx Read/Write pointer's mask */
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#define TXRX_RW_PTR_MASK (ADMA_MAX_TXRX_BD - 1)
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/** Tx/Rx Read/Write pointer's rollover indicate bit */
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#define TXRX_RW_PTR_ROLLOVER_IND ADMA_MAX_TXRX_BD
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/** Start of packet flag */
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#define ADMA_BD_FLAG_SOP MBIT(0)
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/** End of packet flag */
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#define ADMA_BD_FLAG_EOP MBIT(1)
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/** interrupt enable flag */
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#define ADMA_BD_FLAG_INT_EN MBIT(2)
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/** Source address is host side flag */
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#define ADMA_BD_FLAG_SRC_HOST MBIT(3)
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/** Destination address is host side flag */
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#define ADMA_BD_FLAG_DST_HOST MBIT(4)
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/** ADMA MIN PKT SIZE */
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#define ADMA_MIN_PKT_SIZE 128
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/** ADMA dual descriptor mode requir 8 bytes alignment in buf size */
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#define ADMA_ALIGN_SIZE 8
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/** ADMA RW_PTR wrap mask */
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#define ADMA_RW_PTR_WRAP_MASK 0x00001FFF
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/** ADMA MSIX DOORBEEL DATA */
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#define ADMA_MSIX_DOORBELL_DATA 0x0064
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/** MSIX VECTOR MASK: BIT 0-10 */
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#define ADMA_MSIX_VECTOR_MASK 0x3f
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/** PF mask: BIT 24-28 */
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#define ADMA_MSIX_PF_MASK 0x1f000000
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/** PF start bit */
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#define ADMA_MSIX_PF_BIT 24
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#if defined(PCIE9098) || defined(PCIE9097) || defined(PCIENW62X)
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/** PCIE9098 dev_id/vendor id reg */
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#define PCIE9098_DEV_ID_REG 0x0000
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/** PCIE revision ID register */
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#define PCIE9098_REV_ID_REG 0x0008
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/** PCIE IP revision register */
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#define PCIE9098_IP_REV_REG 0x1000
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/** PCIE CPU interrupt events */
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#define PCIE9098_CPU_INT_EVENT 0x1C20
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/** PCIE CPU interrupt status */
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#define PCIE9098_CPU_INT_STATUS 0x1C24
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/** PCIe CPU Interrupt Status Mask */
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#define PCIE9098_CPU_INT2ARM_ISM 0x1C28
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/** PCIE host interrupt status */
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#define PCIE9098_HOST_INT_STATUS 0x1C44
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/** PCIE host interrupt mask */
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#define PCIE9098_HOST_INT_MASK 0x1C48
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/** PCIE host interrupt clear select*/
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#define PCIE9098_HOST_INT_CLR_SEL 0x1C4C
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/** PCIE host interrupt status mask */
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#define PCIE9098_HOST_INT_STATUS_MASK 0x1C50
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/** PCIE host interrupt status */
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#define PCIE9097_B0_HOST_INT_STATUS 0x3C44
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/** PCIE host interrupt mask */
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#define PCIE9097_B0_HOST_INT_MASK 0x3C48
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/** PCIE host interrupt clear select*/
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#define PCIE9097_B0_HOST_INT_CLR_SEL 0x3C4C
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/** PCIE host interrupt status mask */
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#define PCIE9097_B0_HOST_INT_STATUS_MASK 0x3C50
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/** PCIE host interrupt select*/
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#define PCIE9098_HOST_INT_SEL 0x1C58
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/** PCIE data exchange register 0 */
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#define PCIE9098_SCRATCH_0_REG 0x1C60
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/** PCIE data exchange register 1 */
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#define PCIE9098_SCRATCH_1_REG 0x1C64
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/** PCIE data exchange register 2 */
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#define PCIE9098_SCRATCH_2_REG 0x1C68
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/** PCIE data exchange register 3 */
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#define PCIE9098_SCRATCH_3_REG 0x1C6C
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/** PCIE data exchange register 4 */
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#define PCIE9098_SCRATCH_4_REG 0x1C70
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/** PCIE data exchange register 5 */
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#define PCIE9098_SCRATCH_5_REG 0x1C74
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/** PCIE data exchange register 6 */
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#define PCIE9098_SCRATCH_6_REG 0x1C78
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/** PCIE data exchange register 7 */
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#define PCIE9098_SCRATCH_7_REG 0x1C7C
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/** PCIE data exchange register 8 */
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#define PCIE9098_SCRATCH_8_REG 0x1C80
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/** PCIE data exchange register 9 */
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#define PCIE9098_SCRATCH_9_REG 0x1C84
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/** PCIE data exchange register 10 */
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#define PCIE9098_SCRATCH_10_REG 0x1C88
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/** PCIE data exchange register 11 */
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#define PCIE9098_SCRATCH_11_REG 0x1C8C
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/** PCIE data exchange register 12 */
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#define PCIE9098_SCRATCH_12_REG 0x1C90
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/** PCIE data exchange register 13 */
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#define PCIE9098_SCRATCH_13_REG 0x1C94
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/** PCIE data exchange register 14 */
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#define PCIE9098_SCRATCH_14_REG 0x1C98
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/** PCIE data exchange register 15 */
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#define PCIE9098_SCRATCH_15_REG 0x1C9C
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/** ADMA CHAN0_Q0 start address, Tx Data */
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#define ADMA_CHAN0_Q0 0x10000
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/** ADMA CHAN1_Q0 start address, Rx Data */
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#define ADMA_CHAN1_Q0 0x10800
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/** ADMA CHAN1_Q1 start address, Rx Event */
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#define ADMA_CHAN1_Q1 0x10880
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/** ADMA CHAN2_Q0 start address, Tx Command */
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#define ADMA_CHAN2_Q0 0x11000
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/** ADMA CHAN2_Q1 start address, Command Resp */
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#define ADMA_CHAN2_Q1 0x11080
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/** CH0-Q0' src rd/wr ptr */
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#define ADMA_SRC_PTR_CH0_Q0 (ADMA_CHAN0_Q0 + ADMA_SRC_RW_PTR)
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/** CH1-Q1' dest rd/wr ptr */
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#define ADMA_DST_PTR_CH1_Q0 (ADMA_CHAN1_Q0 + ADMA_DST_RW_PTR)
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/** CH1-Q1' dest rd/wr ptr */
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#define ADMA_DST_PTR_CH1_Q1 (ADMA_CHAN1_Q1 + ADMA_DST_RW_PTR)
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/* TX buffer description read pointer */
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#define PCIE9098_TXBD_RDPTR ADMA_SRC_PTR_CH0_Q0
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/* TX buffer description write pointer */
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#define PCIE9098_TXBD_WRPTR ADMA_SRC_PTR_CH0_Q0
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/* RX buffer description read pointer */
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#define PCIE9098_RXBD_RDPTR ADMA_DST_PTR_CH1_Q0
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/* RX buffer description write pointer */
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#define PCIE9098_RXBD_WRPTR ADMA_DST_PTR_CH1_Q0
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/* Event buffer description read pointer */
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#define PCIE9098_EVTBD_RDPTR ADMA_DST_PTR_CH1_Q1
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/* Event buffer description write pointer */
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#define PCIE9098_EVTBD_WRPTR ADMA_DST_PTR_CH1_Q1
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/* Driver ready signature write pointer */
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#define PCIE9098_DRV_READY PCIE9098_SCRATCH_12_REG
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/** interrupt bit define for ADMA CHAN0 Q0, For Tx DATA */
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#define ADMA_INT_CHAN0_Q0 MBIT(0)
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/** interrupt bit define for ADMA CHAN1 Q0, For Rx Data */
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#define AMDA_INT_CHAN1_Q0 MBIT(16)
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/** interrupt bit define for ADMA CHAN1 Q1, For Rx Event */
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#define AMDA_INT_CHAN1_Q1 MBIT(17)
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/** interrupt bit define for ADMA CHAN2 Q0, For Tx Command */
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#define AMDA_INT_CHAN2_Q0 MBIT(24)
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/** interrupt bit define for ADMA CHAN2 Q1, For Rx Command Resp */
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#define AMDA_INT_CHAN2_Q1 MBIT(25)
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/** interrupt vector number for ADMA CHAN0 Q0, For Tx DATA */
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#define ADMA_VECTOR_CHAN0_Q0 0
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/** interrupt vector number for ADMA CHAN1 Q0, For Rx Data */
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#define AMDA_VECTOR_CHAN1_Q0 16
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/** interrupt vector number for ADMA CHAN1 Q1, For Rx Event */
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#define AMDA_VECTOR_CHAN1_Q1 17
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/** interrupt vector number for ADMA CHAN2 Q0, For Tx Command */
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#define AMDA_VECTOR_CHAN2_Q0 24
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/** interrupt vector number for ADMA CHAN2 Q1, For Rx Command Resp */
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#define AMDA_VECTOR_CHAN2_Q1 25
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/** Data sent interrupt for host */
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#define PCIE9098_HOST_INTR_DNLD_DONE ADMA_INT_CHAN0_Q0
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/** Data receive interrupt for host */
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#define PCIE9098_HOST_INTR_UPLD_RDY AMDA_INT_CHAN1_Q0
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/** Command sent interrupt for host */
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#define PCIE9098_HOST_INTR_CMD_DONE AMDA_INT_CHAN2_Q1
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/** Event ready interrupt for host */
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#define PCIE9098_HOST_INTR_EVENT_RDY AMDA_INT_CHAN1_Q1
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/** CMD sent interrupt for host */
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#define PCIE9098_HOST_INTR_CMD_DNLD MBIT(7)
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/** Interrupt mask for host */
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#define PCIE9098_HOST_INTR_MASK \
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(PCIE9098_HOST_INTR_DNLD_DONE | PCIE9098_HOST_INTR_UPLD_RDY | \
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PCIE9098_HOST_INTR_CMD_DONE | PCIE9098_HOST_INTR_CMD_DNLD | \
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PCIE9098_HOST_INTR_EVENT_RDY)
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/** Interrupt select mask for host */
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#define PCIE9098_HOST_INTR_SEL_MASK \
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(PCIE9098_HOST_INTR_DNLD_DONE | PCIE9098_HOST_INTR_UPLD_RDY | \
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PCIE9098_HOST_INTR_CMD_DONE | PCIE9098_HOST_INTR_EVENT_RDY)
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#endif
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#if defined(PCIE8997) || defined(PCIE8897)
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/* PCIE INTERNAL REGISTERS */
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/** PCIE data exchange register 0 */
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#define PCIE_SCRATCH_0_REG 0x0C10
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/** PCIE data exchange register 1 */
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#define PCIE_SCRATCH_1_REG 0x0C14
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/** PCIE CPU interrupt events */
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#define PCIE_CPU_INT_EVENT 0x0C18
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/** PCIE CPU interrupt status */
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#define PCIE_CPU_INT_STATUS 0x0C1C
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/** PCIe CPU Interrupt Status Mask */
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#define PCIE_CPU_INT2ARM_ISM 0x0C28
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/** PCIE host interrupt status */
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#define PCIE_HOST_INT_STATUS 0x0C30
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/** PCIE host interrupt mask */
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#define PCIE_HOST_INT_MASK 0x0C34
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/** PCIE host interrupt status mask */
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#define PCIE_HOST_INT_STATUS_MASK 0x0C3C
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/** PCIE data exchange register 2 */
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#define PCIE_SCRATCH_2_REG 0x0C40
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/** PCIE data exchange register 3 */
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#define PCIE_SCRATCH_3_REG 0x0C44
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#define PCIE_IP_REV_REG 0x0C48
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/** PCIE data exchange register 4 */
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#define PCIE_SCRATCH_4_REG 0x0CD0
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/** PCIE data exchange register 5 */
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#define PCIE_SCRATCH_5_REG 0x0CD4
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/** PCIE data exchange register 6 */
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#define PCIE_SCRATCH_6_REG 0x0CD8
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/** PCIE data exchange register 7 */
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#define PCIE_SCRATCH_7_REG 0x0CDC
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/** PCIE data exchange register 8 */
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#define PCIE_SCRATCH_8_REG 0x0CE0
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/** PCIE data exchange register 9 */
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#define PCIE_SCRATCH_9_REG 0x0CE4
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/** PCIE data exchange register 10 */
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#define PCIE_SCRATCH_10_REG 0x0CE8
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/** PCIE data exchange register 11 */
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#define PCIE_SCRATCH_11_REG 0x0CEC
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/** PCIE data exchange register 12 */
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#define PCIE_SCRATCH_12_REG 0x0CF0
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#endif
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#ifdef PCIE8997
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/* PCIE read data pointer for queue 0 and 1 */
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#define PCIE8997_RD_DATA_PTR_Q0_Q1 0xC1A4 /* 0x8000C1A4 */
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/* PCIE read data pointer for queue 2 and 3 */
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#define PCIE8997_RD_DATA_PTR_Q2_Q3 0xC1A8 /* 0x8000C1A8 */
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/* PCIE write data pointer for queue 0 and 1 */
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#define PCIE8997_WR_DATA_PTR_Q0_Q1 0xC174 /* 0x8000C174 */
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/* PCIE write data pointer for queue 2 and 3 */
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#define PCIE8997_WR_DATA_PTR_Q2_Q3 0xC178 /* 0x8000C178 */
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#endif
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#ifdef PCIE8897
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/* PCIE read data pointer for queue 0 and 1 */
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#define PCIE8897_RD_DATA_PTR_Q0_Q1 0xC08C /* 0x8000C08C */
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/* PCIE read data pointer for queue 2 and 3 */
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#define PCIE8897_RD_DATA_PTR_Q2_Q3 0xC090 /* 0x8000C090 */
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/* PCIE write data pointer for queue 0 and 1 */
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#define PCIE8897_WR_DATA_PTR_Q0_Q1 0xC05C /* 0x8000C05C */
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/* PCIE write data pointer for queue 2 and 3 */
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#define PCIE8897_WR_DATA_PTR_Q2_Q3 0xC060 /* 0x8000C060 */
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#endif
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/** Download ready interrupt for CPU */
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#define CPU_INTR_DNLD_RDY MBIT(0)
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/** Command ready interrupt for CPU */
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#define CPU_INTR_DOOR_BELL MBIT(1)
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/** Confirmation that sleep confirm message has been processed.
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Device will enter sleep after receiving this interrupt */
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#define CPU_INTR_SLEEP_CFM_DONE MBIT(2)
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/** Reset interrupt for CPU */
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#define CPU_INTR_RESET MBIT(3)
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/** Set Event Done interupt to the FW*/
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#define CPU_INTR_EVENT_DONE MBIT(5)
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#if defined(PCIE8997) || defined(PCIE8897)
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/** Data sent interrupt for host */
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#define HOST_INTR_DNLD_DONE MBIT(0)
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/** Data receive interrupt for host */
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#define HOST_INTR_UPLD_RDY MBIT(1)
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/** Command sent interrupt for host */
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#define HOST_INTR_CMD_DONE MBIT(2)
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/** Event ready interrupt for host */
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#define HOST_INTR_EVENT_RDY MBIT(3)
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/** Interrupt mask for host */
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#define HOST_INTR_MASK \
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(HOST_INTR_DNLD_DONE | HOST_INTR_UPLD_RDY | HOST_INTR_CMD_DONE | \
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HOST_INTR_EVENT_RDY)
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/** Lower 32bits command address holding register */
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#define REG_CMD_ADDR_LO PCIE_SCRATCH_0_REG
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/** Upper 32bits command address holding register */
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#define REG_CMD_ADDR_HI PCIE_SCRATCH_1_REG
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/** Command length holding register */
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#define REG_CMD_SIZE PCIE_SCRATCH_2_REG
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/** Lower 32bits command response address holding register */
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#define REG_CMDRSP_ADDR_LO PCIE_SCRATCH_4_REG
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/** Upper 32bits command response address holding register */
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#define REG_CMDRSP_ADDR_HI PCIE_SCRATCH_5_REG
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/** TxBD's Read/Write pointer start from bit 16 */
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#define TXBD_RW_PTR_START 16
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/** RxBD's Read/Write pointer start from bit 0 */
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#define RXBD_RW_PTR_STRAT 0
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#define MLAN_BD_FLAG_SOP MBIT(0)
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#define MLAN_BD_FLAG_EOP MBIT(1)
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#define MLAN_BD_FLAG_XS_SOP MBIT(2)
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#define MLAN_BD_FLAG_XS_EOP MBIT(3)
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/* Event buffer description write pointer */
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#define REG_EVTBD_WRPTR PCIE_SCRATCH_10_REG
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/* Event buffer description read pointer */
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#define REG_EVTBD_RDPTR PCIE_SCRATCH_11_REG
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/* Driver ready signature write pointer */
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#define REG_DRV_READY PCIE_SCRATCH_12_REG
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/** Event Read/Write pointer mask */
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#define EVT_RW_PTR_MASK 0x0f
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/** Event Read/Write pointer rollover bit */
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#define EVT_RW_PTR_ROLLOVER_IND MBIT(7)
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#endif
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/* Define PCIE block size for firmware download */
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#define MLAN_PCIE_BLOCK_SIZE_FW_DNLD 256
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/** Extra added macros **/
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#define MLAN_EVENT_HEADER_LEN 8
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/** Max interrupt status register read limit */
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#define MAX_READ_REG_RETRY 10000
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extern mlan_adapter_operations mlan_pcie_ops;
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/* Get pcie device from card type */
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mlan_status wlan_get_pcie_device(pmlan_adapter pmadapter);
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/** Set PCIE host buffer configurations */
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mlan_status wlan_set_pcie_buf_config(mlan_private *pmpriv);
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|
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/** Init write pointer */
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mlan_status wlan_pcie_init_fw(pmlan_adapter pmadapter);
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|
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#if defined(PCIE8997) || defined(PCIE8897)
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/** Prepare command PCIE host buffer config */
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mlan_status wlan_cmd_pcie_host_buf_cfg(pmlan_private pmpriv,
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pHostCmd_DS_COMMAND cmd,
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t_u16 cmd_action, t_pvoid pdata_buf);
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#endif
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/** Wakeup PCIE card */
|
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mlan_status wlan_pcie_wakeup(pmlan_adapter pmadapter);
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|
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/** Set DRV_READY register */
|
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mlan_status wlan_set_drv_ready_reg(mlan_adapter *pmadapter, t_u32 val);
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/** PCIE init */
|
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mlan_status wlan_pcie_init(mlan_adapter *pmadapter);
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|
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/** Read interrupt status */
|
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mlan_status wlan_process_msix_int(mlan_adapter *pmadapter);
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/** Transfer data to card */
|
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mlan_status wlan_pcie_host_to_card(pmlan_private pmpriv, t_u8 type,
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mlan_buffer *mbuf, mlan_tx_param *tx_param);
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/** Ring buffer allocation function */
|
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mlan_status wlan_alloc_pcie_ring_buf(pmlan_adapter pmadapter);
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/** Ring buffer deallocation function */
|
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mlan_status wlan_free_pcie_ring_buf(pmlan_adapter pmadapter);
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/** Ring buffer cleanup function, e.g. on deauth */
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mlan_status wlan_clean_pcie_ring_buf(pmlan_adapter pmadapter);
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mlan_status wlan_alloc_ssu_pcie_buf(pmlan_adapter pmadapter);
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mlan_status wlan_free_ssu_pcie_buf(pmlan_adapter pmadapter);
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#endif /* _MLAN_PCIE_H_ */
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