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https://github.com/nxp-imx/mwifiex.git
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bd8827d169
The sdk release is from NXP offial web: https://www.nxp.com/products/wireless/wi-fi-plus-bluetooth/ 88w8997-wi-fi-dual-band-with-bluetooth-5-for-a-v-streaming-and-digital-tv:88W8997?tab=Design_Tools_Tab The release file is: PCIE-WLAN-UART-BT-8997-U16-X86-W16.68.10.p16-16.26.10.p16-C4X16640_V4-MGPL The sdk version is: W16.68.10.p16 Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
216 lines
8.6 KiB
C
Executable file
216 lines
8.6 KiB
C
Executable file
/** @file mlan_pcie.h
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*
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* @brief This file contains definitions for PCIE interface.
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* driver.
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*
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* Copyright (C) 2014-2019, Marvell International Ltd.
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*
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* This software file (the "File") is distributed by Marvell International
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* Ltd. under the terms of the GNU General Public License Version 2, June 1991
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* (the "License"). You may use, redistribute and/or modify this File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*/
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/********************************************************
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Change log:
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02/01/2012: initial version
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********************************************************/
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#ifndef _MLAN_PCIE_H_
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#define _MLAN_PCIE_H_
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/* PCIE INTERNAL REGISTERS */
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/** PCIE data exchange register 0 */
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#define PCIE_SCRATCH_0_REG 0x0C10
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/** PCIE data exchange register 1 */
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#define PCIE_SCRATCH_1_REG 0x0C14
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/** PCIE CPU interrupt events */
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#define PCIE_CPU_INT_EVENT 0x0C18
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/** PCIE CPU interrupt status */
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#define PCIE_CPU_INT_STATUS 0x0C1C
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/** PCIe CPU Interrupt Status Mask */
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#define PCIE_CPU_INT2ARM_ISM 0x0C28
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/** PCIE host interrupt status */
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#define PCIE_HOST_INT_STATUS 0x0C30
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/** PCIE host interrupt mask */
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#define PCIE_HOST_INT_MASK 0x0C34
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/** PCIE host interrupt status mask */
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#define PCIE_HOST_INT_STATUS_MASK 0x0C3C
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/** PCIE data exchange register 2 */
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#define PCIE_SCRATCH_2_REG 0x0C40
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/** PCIE data exchange register 3 */
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#define PCIE_SCRATCH_3_REG 0x0C44
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#define PCIE_IP_REV_REG 0x0C48
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/** PCIE data exchange register 4 */
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#define PCIE_SCRATCH_4_REG 0x0CD0
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/** PCIE data exchange register 5 */
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#define PCIE_SCRATCH_5_REG 0x0CD4
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/** PCIE data exchange register 6 */
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#define PCIE_SCRATCH_6_REG 0x0CD8
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/** PCIE data exchange register 7 */
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#define PCIE_SCRATCH_7_REG 0x0CDC
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/** PCIE data exchange register 8 */
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#define PCIE_SCRATCH_8_REG 0x0CE0
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/** PCIE data exchange register 9 */
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#define PCIE_SCRATCH_9_REG 0x0CE4
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/** PCIE data exchange register 10 */
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#define PCIE_SCRATCH_10_REG 0x0CE8
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/** PCIE data exchange register 11 */
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#define PCIE_SCRATCH_11_REG 0x0CEC
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/** PCIE data exchange register 12 */
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#define PCIE_SCRATCH_12_REG 0x0CF0
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/* PCIE read data pointer for queue 0 and 1 */
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#define PCIE_RD_DATA_PTR_Q0_Q1 0xC1A4 /* 0x8000C1A4 */
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/* PCIE read data pointer for queue 2 and 3 */
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#define PCIE_RD_DATA_PTR_Q2_Q3 0xC1A8 /* 0x8000C1A8 */
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/* PCIE write data pointer for queue 0 and 1 */
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#define PCIE_WR_DATA_PTR_Q0_Q1 0xC174 /* 0x8000C174 */
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/* PCIE write data pointer for queue 2 and 3 */
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#define PCIE_WR_DATA_PTR_Q2_Q3 0xC178 /* 0x8000C178 */
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/** Download ready interrupt for CPU */
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#define CPU_INTR_DNLD_RDY MBIT(0)
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/** Command ready interrupt for CPU */
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#define CPU_INTR_DOOR_BELL MBIT(1)
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/** Confirmation that sleep confirm message has been processed.
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Device will enter sleep after receiving this interrupt */
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#define CPU_INTR_SLEEP_CFM_DONE MBIT(2)
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/** Reset interrupt for CPU */
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#define CPU_INTR_RESET MBIT(3)
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/** Set Event Done interupt to the FW*/
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#define CPU_INTR_EVENT_DONE MBIT(5)
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/** Data sent interrupt for host */
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#define HOST_INTR_DNLD_DONE MBIT(0)
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/** Data receive interrupt for host */
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#define HOST_INTR_UPLD_RDY MBIT(1)
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/** Command sent interrupt for host */
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#define HOST_INTR_CMD_DONE MBIT(2)
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/** Event ready interrupt for host */
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#define HOST_INTR_EVENT_RDY MBIT(3)
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/** Interrupt mask for host */
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#define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \
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HOST_INTR_UPLD_RDY | \
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HOST_INTR_CMD_DONE | \
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HOST_INTR_EVENT_RDY)
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/** Lower 32bits command address holding register */
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#define REG_CMD_ADDR_LO PCIE_SCRATCH_0_REG
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/** Upper 32bits command address holding register */
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#define REG_CMD_ADDR_HI PCIE_SCRATCH_1_REG
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/** Command length holding register */
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#define REG_CMD_SIZE PCIE_SCRATCH_2_REG
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/** Lower 32bits command response address holding register */
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#define REG_CMDRSP_ADDR_LO PCIE_SCRATCH_4_REG
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/** Upper 32bits command response address holding register */
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#define REG_CMDRSP_ADDR_HI PCIE_SCRATCH_5_REG
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/* TX buffer description read pointer */
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#define REG_TXBD_RDPTR PCIE_RD_DATA_PTR_Q0_Q1
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/* TX buffer description write pointer */
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#define REG_TXBD_WRPTR PCIE_WR_DATA_PTR_Q0_Q1
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/* TX buffer 2 description read pointer */
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#define REG_TXBD2_RDPTR PCIE_RD_DATA_PTR_Q2_Q3
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/* TX buffer 2 description write pointer */
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#define REG_TXBD2_WRPTR PCIE_WR_DATA_PTR_Q2_Q3
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/* RX buffer description write pointer */
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#define REG_RXBD_WRPTR PCIE_WR_DATA_PTR_Q0_Q1
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/* RX buffer description read pointer */
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#define REG_RXBD_RDPTR PCIE_RD_DATA_PTR_Q0_Q1
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/** TxBD's Read/Write pointer start from bit 16 */
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#define TXBD_RW_PTR_START 16
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/** RxBD's Read/Write pointer start from bit 0 */
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#define RXBD_RW_PTR_STRAT 0
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/** Tx/Rx Read/Write pointer's mask */
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#define TXRX_RW_PTR_MASK 0x00000FFF
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/** Tx/Rx Read/Write pointer's wrap mask */
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#define TXRX_RW_PTR_WRAP_MASK 0x00001FFF
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/** Tx/Rx Read/Write pointer's rollover indicate bit */
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#define TXRX_RW_PTR_ROLLOVER_IND MBIT(12)
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#define MLAN_BD_FLAG_SOP MBIT(0)
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#define MLAN_BD_FLAG_EOP MBIT(1)
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#define MLAN_BD_FLAG_XS_SOP MBIT(2)
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#define MLAN_BD_FLAG_XS_EOP MBIT(3)
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#define REG_EVTBD_WRPTR PCIE_SCRATCH_10_REG
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/* Event buffer description read pointer */
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#define REG_EVTBD_RDPTR PCIE_SCRATCH_11_REG
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/* Driver ready signature write pointer */
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#define REG_DRV_READY PCIE_SCRATCH_12_REG
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/** Event Read/Write pointer mask */
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#define EVT_RW_PTR_MASK 0x0f
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/** Event Read/Write pointer rollover bit */
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#define EVT_RW_PTR_ROLLOVER_IND MBIT(7)
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/* Define PCIE block size for firmware download */
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#define MLAN_PCIE_BLOCK_SIZE_FW_DNLD 256
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/** Extra added macros **/
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#define MLAN_EVENT_HEADER_LEN 8
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/** Max interrupt status register read limit */
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#define MAX_READ_REG_RETRY 10000
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/** Set PCIE host buffer configurations */
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mlan_status wlan_set_pcie_buf_config(mlan_private *pmpriv);
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/** Prepare command PCIE host buffer config */
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mlan_status wlan_cmd_pcie_host_buf_cfg(pmlan_private pmpriv,
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IN HostCmd_DS_COMMAND *cmd,
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IN t_u16 cmd_action,
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IN t_void *pdata_buf);
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/** Wakeup PCIE card */
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mlan_status wlan_pcie_wakeup(mlan_adapter *pmadapter);
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/** Enable host interrupt */
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mlan_status wlan_enable_host_int(pmlan_adapter pmadapter);
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/** PCIE command response completion function */
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mlan_status wlan_pcie_cmdrsp_complete(mlan_adapter *pmadapter,
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mlan_buffer *pmbuf);
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/** PCIE event completion function */
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mlan_status wlan_pcie_event_complete(mlan_adapter *pmadapter,
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mlan_buffer *pmbuf);
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/** Set DRV_READY register */
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mlan_status wlan_set_drv_ready_reg(mlan_adapter *pmadapter, t_u32 val);
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/** multi interface download check */
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mlan_status wlan_check_winner_status(mlan_adapter *pmadapter, t_u32 *val);
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/** Firmware status check */
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mlan_status wlan_check_fw_status(mlan_adapter *pmadapter, t_u32 pollnum);
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/** PCIE init */
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mlan_status wlan_pcie_init(mlan_adapter *pmadapter);
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/** Init Firmware */
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mlan_status wlan_pcie_init_fw(pmlan_adapter pmadapter);
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/** Read interrupt status */
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mlan_status wlan_interrupt(t_u16 msg_id, pmlan_adapter pmadapter);
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mlan_status wlan_process_msix_int(mlan_adapter *pmadapter);
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/** Process Interrupt Status */
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mlan_status wlan_process_int_status(mlan_adapter *pmadapter);
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/** Transfer data to card */
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mlan_status wlan_pcie_host_to_card(mlan_adapter *pmadapter, t_u8 type,
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mlan_buffer *mbuf, mlan_tx_param *tx_param);
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/** Ring buffer allocation function */
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mlan_status wlan_alloc_pcie_ring_buf(pmlan_adapter pmadapter);
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/** Ring buffer deallocation function */
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mlan_status wlan_free_pcie_ring_buf(pmlan_adapter pmadapter);
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/** Ring buffer cleanup function, e.g. on deauth */
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mlan_status wlan_clean_pcie_ring_buf(pmlan_adapter pmadapter);
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#endif /* _MLAN_PCIE_H_ */
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