#CYW4356 1CX WLCSP module for iPA, eLNA board with PCIE for production package
NVRAMRev=$Rev: 373428 $
sromrev=11
boardrev=0x1202
## boardtype is subject to change
boardtype=0x0735
boardflags=0x12401001
#enable eLNA both 2G/5G
boardflags2=0x00802000
boardflags3=0x48000189
#boardnum=57410 
macaddr=00:90:4c:16:70:01
ccode=0
regrev=0
antswitch=0
pdgain5g=4
pdgain2g=4
tworangetssi2g=0
tworangetssi5g=0
femctrl=10
vendid=0x14e4
devid=0x43ec
manfid=0x2d0
#prodid=0x052e
nocrc=1
otpimagesize=484
xtalfreq=37400
rxgains2gelnagaina0=2
rxgains2gtrisoa0=6
rxgains2gtrelnabypa0=1
rxgains5gelnagaina0=2
rxgains5gtrisoa0=6
rxgains5gtrelnabypa0=1
rxgains5gmelnagaina0=2
rxgains5gmtrisoa0=6
rxgains5gmtrelnabypa0=1
rxgains5ghelnagaina0=2
rxgains5ghtrisoa0=6
rxgains5ghtrelnabypa0=1
rxgains2gelnagaina1=2
rxgains2gtrisoa1=6
rxgains2gtrelnabypa1=1
rxgains5gelnagaina1=2
rxgains5gtrisoa1=6
rxgains5gtrelnabypa1=1
rxgains5gmelnagaina1=2
rxgains5gmtrisoa1=6
rxgains5gmtrelnabypa1=1
rxgains5ghelnagaina1=2
rxgains5ghtrisoa1=6
rxgains5ghtrelnabypa1=1
rxchain=3
txchain=3
ag0=1
ag1=1
## aa2g/aa5g should be set to 3
aa2g=3
aa5g=3
agbg0=2
agbg1=2
aga0=2
aga1=2
tssipos2g=1
extpagain2g=2
tssipos5g=1
extpagain5g=2
tempthresh=120
temps_hysteresis=15
tempoffset=255
rawtempsense=0x1ff
pa2gccka0=-122,7046,-772
pa2gccka1=-139,6542,-744
pa2ga0=-155,6342,-721
pa2ga1=-120,6288,-674
pa5ga0=-183,5892,-714,-181,5916,-712,-196,5769,-706,-191,5880,-714
pa5ga1=-193,5954,-725,-194,5958,-728,-194,6078,-742,-199,5913,-727
maxp2ga0=78
maxp5ga0=74,74,74,74
maxp2ga1=78
maxp5ga1=74,74,74,74
subband5gver=0x4
pdoffsetcckma0=0x0
pdoffsetcckma1=0x0
#pdoffsetcckma0=0x4
#pdoffsetcckma1=0x4
pdoffset40ma0=0x0000
pdoffset80ma0=0x0000
pdoffset40ma1=0x0000
pdoffset80ma1=0x0000
cckbw202gpo=0x0000
cckbw20ul2gpo=0x0000
mcsbw202gpo=0xccaaaaaa
mcsbw402gpo=0xaaaaaaaa
dot11agofdmhrbw202gpo=0x6666
ofdmlrbw202gpo=0xaa66
mcsbw205glpo=0xca888888
mcsbw405glpo=0xca888888
mcsbw805glpo=0xcccccccc
mcsbw205gmpo=0xca888888
mcsbw405gmpo=0xca888888
mcsbw805gmpo=0xcccccccc
mcsbw205ghpo=0xca888888
mcsbw405ghpo=0xca888888
mcsbw805ghpo=0xcccccccc
mcslr5glpo=0x0000
mcslr5gmpo=0x0000
mcslr5ghpo=0x0000
sb20in40hrpo=0x0
sb20in80and160hr5glpo=0x0
sb40and80hr5glpo=0x0
sb20in80and160hr5gmpo=0x0
sb40and80hr5gmpo=0x0
sb20in80and160hr5ghpo=0x0
sb40and80hr5ghpo=0x0
sb20in40lrpo=0x0
sb20in80and160lr5glpo=0x0
sb40and80lr5glpo=0x0
sb20in80and160lr5gmpo=0x0
sb40and80lr5gmpo=0x0
sb20in80and160lr5ghpo=0x0
sb40and80lr5ghpo=0x0
dot11agduphrpo=0x0
dot11agduplrpo=0x0
phycal_tempdelta=25
temps_period=15
AvVmid_c0=2,140,2,145,2,145,2,145,2,145
AvVmid_c1=2,140,2,145,2,145,2,145,2,145
rssicorrnorm_c0=0,0
rssicorrnorm_c1=0,0
rssicorrnorm5g_c0=1,2,2,1,2,2,1,2,3,1,2,3
rssicorrnorm5g_c1=2,3,4,2,3,4,0,1,2,0,1,2
epsdelta2g0=0
epsdelta2g1=0
ofdmfilttype=1
##cckfilttype
#cckdigfilttype=2
cckdigfilttype=5
phy4350_ss_opt=1
## SWCTRL map changed - 8/29
swctrlmap_5g=0x02020202,0x05050404,0x04040000,0x000000,0x047
swctrlmap_2g=0x140c140c,0x28300820,0x08200000,0x803020,0x0ff
## muxenab to enable OOB signal - needed for final board
#muxenab=0x11
## to improve ACPR for low rates in 2GHz
papdwar=4
## to improve current consumption in tx
tssisleep_en=0x1f