mirror of
https://github.com/NXP/imx-firmware.git
synced 2024-11-16 01:15:35 +00:00
148 lines
3.1 KiB
Text
148 lines
3.1 KiB
Text
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#CYW4356 1CX WLCSP module for iPA, eLNA board with PCIE for production package
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NVRAMRev=$Rev: 373428 $
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sromrev=11
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boardrev=0x1202
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## boardtype is subject to change
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boardtype=0x0735
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boardflags=0x12401001
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#enable eLNA both 2G/5G
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boardflags2=0x00802000
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boardflags3=0x48000189
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#boardnum=57410
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macaddr=00:90:4c:16:70:01
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ccode=0
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regrev=0
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antswitch=0
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pdgain5g=4
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pdgain2g=4
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tworangetssi2g=0
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tworangetssi5g=0
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femctrl=10
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vendid=0x14e4
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devid=0x43ec
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manfid=0x2d0
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#prodid=0x052e
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nocrc=1
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otpimagesize=484
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xtalfreq=37400
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rxgains2gelnagaina0=2
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rxgains2gtrisoa0=6
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rxgains2gtrelnabypa0=1
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rxgains5gelnagaina0=2
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rxgains5gtrisoa0=6
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rxgains5gtrelnabypa0=1
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rxgains5gmelnagaina0=2
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rxgains5gmtrisoa0=6
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rxgains5gmtrelnabypa0=1
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rxgains5ghelnagaina0=2
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rxgains5ghtrisoa0=6
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rxgains5ghtrelnabypa0=1
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rxgains2gelnagaina1=2
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rxgains2gtrisoa1=6
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rxgains2gtrelnabypa1=1
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rxgains5gelnagaina1=2
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rxgains5gtrisoa1=6
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rxgains5gtrelnabypa1=1
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rxgains5gmelnagaina1=2
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rxgains5gmtrisoa1=6
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rxgains5gmtrelnabypa1=1
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rxgains5ghelnagaina1=2
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rxgains5ghtrisoa1=6
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rxgains5ghtrelnabypa1=1
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rxchain=3
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txchain=3
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ag0=1
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ag1=1
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## aa2g/aa5g should be set to 3
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aa2g=3
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aa5g=3
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agbg0=2
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agbg1=2
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aga0=2
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aga1=2
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tssipos2g=1
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extpagain2g=2
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tssipos5g=1
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extpagain5g=2
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tempthresh=120
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temps_hysteresis=15
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tempoffset=255
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rawtempsense=0x1ff
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pa2gccka0=-122,7046,-772
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pa2gccka1=-139,6542,-744
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pa2ga0=-155,6342,-721
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pa2ga1=-120,6288,-674
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pa5ga0=-183,5892,-714,-181,5916,-712,-196,5769,-706,-191,5880,-714
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pa5ga1=-193,5954,-725,-194,5958,-728,-194,6078,-742,-199,5913,-727
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maxp2ga0=78
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maxp5ga0=74,74,74,74
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maxp2ga1=78
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maxp5ga1=74,74,74,74
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subband5gver=0x4
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pdoffsetcckma0=0x0
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pdoffsetcckma1=0x0
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#pdoffsetcckma0=0x4
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#pdoffsetcckma1=0x4
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pdoffset40ma0=0x0000
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pdoffset80ma0=0x0000
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pdoffset40ma1=0x0000
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pdoffset80ma1=0x0000
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cckbw202gpo=0x0000
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cckbw20ul2gpo=0x0000
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mcsbw202gpo=0xccaaaaaa
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mcsbw402gpo=0xaaaaaaaa
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dot11agofdmhrbw202gpo=0x6666
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ofdmlrbw202gpo=0xaa66
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mcsbw205glpo=0xca888888
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mcsbw405glpo=0xca888888
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mcsbw805glpo=0xcccccccc
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mcsbw205gmpo=0xca888888
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mcsbw405gmpo=0xca888888
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mcsbw805gmpo=0xcccccccc
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mcsbw205ghpo=0xca888888
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mcsbw405ghpo=0xca888888
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mcsbw805ghpo=0xcccccccc
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mcslr5glpo=0x0000
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mcslr5gmpo=0x0000
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mcslr5ghpo=0x0000
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sb20in40hrpo=0x0
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sb20in80and160hr5glpo=0x0
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sb40and80hr5glpo=0x0
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sb20in80and160hr5gmpo=0x0
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sb40and80hr5gmpo=0x0
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sb20in80and160hr5ghpo=0x0
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sb40and80hr5ghpo=0x0
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sb20in40lrpo=0x0
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sb20in80and160lr5glpo=0x0
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sb40and80lr5glpo=0x0
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sb20in80and160lr5gmpo=0x0
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sb40and80lr5gmpo=0x0
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sb20in80and160lr5ghpo=0x0
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sb40and80lr5ghpo=0x0
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dot11agduphrpo=0x0
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dot11agduplrpo=0x0
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phycal_tempdelta=25
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temps_period=15
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AvVmid_c0=2,140,2,145,2,145,2,145,2,145
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AvVmid_c1=2,140,2,145,2,145,2,145,2,145
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rssicorrnorm_c0=0,0
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rssicorrnorm_c1=0,0
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rssicorrnorm5g_c0=1,2,2,1,2,2,1,2,3,1,2,3
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rssicorrnorm5g_c1=2,3,4,2,3,4,0,1,2,0,1,2
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epsdelta2g0=0
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epsdelta2g1=0
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ofdmfilttype=1
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##cckfilttype
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#cckdigfilttype=2
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cckdigfilttype=5
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phy4350_ss_opt=1
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## SWCTRL map changed - 8/29
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swctrlmap_5g=0x02020202,0x05050404,0x04040000,0x000000,0x047
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swctrlmap_2g=0x140c140c,0x28300820,0x08200000,0x803020,0x0ff
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## muxenab to enable OOB signal - needed for final board
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#muxenab=0x11
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## to improve ACPR for low rates in 2GHz
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papdwar=4
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## to improve current consumption in tx
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tssisleep_en=0x1f
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