110 lines
4.0 KiB
Diff
110 lines
4.0 KiB
Diff
author Stephen Boyd <sboyd@codeaurora.org> 2015-03-20 23:45:22 -0700
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committer John Stultz <john.stultz@linaro.org> 2017-05-12 14:09:21 -0700
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commit a4daa927877f99711d1d90eb4ecbef9655ae7071 (patch)
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tree 60d791c89659daf488265681a0e98f288f5168a7
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parent d337a84d6b6adc6d7e315de7faba6694bb25b05e (diff)
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download flo-a4daa927877f99711d1d90eb4ecbef9655ae7071.tar.gz
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clk: Avoid sending high rates to downstream clocks during set_rate
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If a clock is on and we call clk_set_rate() on it we may get into
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a situation where the clock temporarily increases in rate
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dramatically while we walk the tree and call .set_rate() ops. For
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example, consider a case where a PLL feeds into a divider.
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Initially the divider is set to divide by 1 and the PLL is
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running fairly slow (100MHz). The downstream consumer of the
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divider output can only handle rates =< 400 MHz, but the divider
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can only choose between divisors of 1 and 4.
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+-----+ +----------------+
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| PLL |-->| div 1 or div 4 |---> consumer device
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+-----+ +----------------+
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To achieve a rate of 400MHz on the output of the divider, we
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would have to set the rate of the PLL to 1.6 GHz and then divide
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it by 4. The current code would set the PLL to 1.6GHz first while
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the divider is still set to 1, thus causing the downstream
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consumer of the clock to receive a few clock cycles of 1.6GHz
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clock (far beyond it's maximum acceptable rate). We should be
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changing the divider first before increasing the PLL rate to
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avoid this problem.
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Therefore, set the rate of any child clocks that are increasing
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in rate from their current rate so that they can increase their
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dividers if necessary. We assume that there isn't such a thing as
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minimum rate requirements.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Conflicts:
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drivers/clk/clk.c
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Diffstat
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-rw-r--r-- drivers/clk/clk.c 22
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1 files changed, 15 insertions, 7 deletions
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diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
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index fc58c52..784d7a2 100644
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--- a/drivers/clk/clk.c
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+++ b/drivers/clk/clk.c
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@@ -1468,12 +1468,12 @@ static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
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* walk down a subtree and set the new rates notifying the rate
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* change on the way
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*/
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-static void clk_change_rate(struct clk_core *core)
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+static void
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+clk_change_rate(struct clk_core *core, unsigned long best_parent_rate)
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{
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struct clk_core *child;
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struct hlist_node *tmp;
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unsigned long old_rate;
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- unsigned long best_parent_rate = 0;
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bool skip_set_rate = false;
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struct clk_core *old_parent;
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struct clk_core *parent = NULL;
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@@ -1525,6 +1525,7 @@ static void clk_change_rate(struct clk_core *core)
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trace_clk_set_rate_complete(core, core->new_rate);
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core->rate = clk_recalc(core, best_parent_rate);
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+ core->rate = core->new_rate;
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if (core->flags & CLK_SET_RATE_UNGATE) {
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unsigned long flags;
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@@ -1552,12 +1553,13 @@ static void clk_change_rate(struct clk_core *core)
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/* Skip children who will be reparented to another clock */
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if (child->new_parent && child->new_parent != core)
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continue;
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- clk_change_rate(child);
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+ if (child->new_rate != child->rate)
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+ clk_change_rate(child, core->new_rate);
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}
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- /* handle the new child who might not be in core->children yet */
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- if (core->new_child)
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- clk_change_rate(core->new_child);
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+ /* handle the new child who might not be in clk->children yet */
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+ if (core->new_child && core->new_child->new_rate != core->new_child->rate)
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+ clk_change_rate(core->new_child, core->new_rate);
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}
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static int clk_core_set_rate_nolock(struct clk_core *core,
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@@ -1565,6 +1567,7 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
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{
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struct clk_core *top, *fail_clk;
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unsigned long rate = req_rate;
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+ unsigned long parent_rate;
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if (!core)
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return 0;
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@@ -1590,8 +1593,13 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
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return -EBUSY;
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}
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+ if (top->parent)
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+ parent_rate = top->parent->rate;
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+ else
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+ parent_rate = 0;
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+
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/* change the rates */
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- clk_change_rate(top);
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+ clk_change_rate(top, parent_rate);
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core->req_rate = req_rate;
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